1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method for the semiconductor device. In particular, the present invention relates to a semiconductor device and a fabrication method for the semiconductor device provided with a package of a wafer level, in a package of a high frequency semiconductor device.
2. Description of the Related Art
In a field effect transistor applied to a high frequency semiconductor device, in order to keep airtightness, packaging is achieved by placing a semiconductor device, a matching circuit, etc. in housing composed of metal, ceramics, etc.
However, the cost concerning the housing of this package was large, and this had become an obstacle of low-pricing in the cost aspect of the semiconductor device. Moreover, in potting by resin etc., the problem that gain reduction occurred by the increase in capacity of a gate electrode had occurred.
As technology for solving this problem, a wafer level packaging which can keep the airtightness to the semiconductor device itself with a hollow protective film, and can reduce the capacity of a gate electrode is developed and filed as patent application by the present applicant (Japanese Patent Application No. P2008-013721).
However, since the volume of hollow sections was large in order to wrap an active part of the field effect transistor by using this technology, there was a problem that it is anxious about the mechanical strength of the protective film.
On the other hand, in order to reduce the increase in the capacity by a passivation film, a semiconductor device and a fabrication method for the semiconductor device which provided a hollow area between the passivation film and a metal electrode which a high frequency signal outputs and inputs, is already disclosed (for example, refer to Patent Document 1).
On the other hand, a semiconductor device and a fabrication method for the semiconductor device which reduces the parasitic capacitance between a source electrode or a drain electrode, and a gate electrode, and improves high frequency characteristics by removing an insulating film under the eaves of the gate electrode toward a mold are already disclosed (for example, refer to Patent Document 2).    Patent document 1:
Japanese Patent Application Laying-Open Publication No. H06-140440    Patent document 2:
Japanese Patent Application Laying-Open Publication No. H11-354540